? semiconductor components industries, llc, 2015 september, 2015 ? rev. 2 1 publication order number: esd7361/d esd7361, szesd7361 esd protection diodes low capacitance esd protection diode for high speed data line the esd7361 series esd protection diodes are designed to protect high speed data lines from esd. ultra?low capacitance make this device an ideal solution for protecting voltage sensitive high speed data lines. features ? low capacitance (0.55 pf max, i/o to gnd) ? protection for the following iec standards: ? iec61000?4?2 (esd): level 4 15 kv contact ? iec61000?4?4 (eft): 40 a ?5/50 ns ? iec61000?4?5 (lightning): 1 a (8/20 s) ? iso 10605 (esd) 330 pf/2 k 15 kv contact ? sz prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? wireless charger ? near field communications maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j ?55 to +125 c storage temperature range t stg ?55 to +150 c lead solder temperature ? maximum (10 seconds) t l 260 c iec 61000?4?2 contact (esd) iec 61000?4?2 air (esd) iso 10605 330 pf/2 k contact (esd) esd esd esd 15 15 15 kv kv kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. marking diagrams pin configuration and schematic www. onsemi.com x, xx = specific device code m = date code 1 cathode 2 anode sod?323 case 477 sod?523 case 502 sod?923 case 514ab 1 2 7h m 1 2 7x 12 m 2 m see detailed ordering and shipping information on page 6 o f this data sheet. ordering information
esd7361, szesd7361 www. onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current *see application note and8308/d for detailed explanations of datasheet parameters. uni?directional tvs i pp i f v i i r i t v rwm v c v br v f electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm 5 16 v breakdown voltage v br i t = 1 ma; pin 1 to pin 2 16.5 v reverse leakage current i r v rwm = 5.0 v <1 1000 na clamping voltage (note 2) v c i pp = 8 a 31 v clamping voltage (note 2) v c i pp = 16 a 34 v junction capacitance c j v r = 0 v, f = 1 mhz v r = 0 v, f < 1 ghz 0.55 0.55 pf dynamic resistance r dyn tlp pulse 0.735 insertion loss f = 1 mhz f = 5 ghz 0.01 2 db product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. for test procedure see figures 9 and 10 and application note and8307/d. 2. ansi/esd stm5.5.1 ? electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. figure 1. typical iv characteristics figure 2. typical cv characteristics 1.e?03 1.e?04 1.e?05 1.e?06 1.e?07 1.e?08 1.e?09 1.e?10 1.e?11 1.e?12 1.e?13 0 5 10 15 20 25 30 voltage (v) current (a) v bias (v) capacitance (pf) 1 0.8 0.6 0.4 0.2 0 04 8 14 18 2 61012 16
esd7361, szesd7361 www. onsemi.com 3 figure 3. typical insertion loss ESD7361HT1G (sod323) figure 4. typical capacitance over frequency ESD7361HT1G (sod323) s21 (db) frequency (hz) capacitance (pf) frequency (hz) 1 1.e+07 1.e+08 1.e+09 1 1.e+07 5.e+08 1.e+09 2.e+09 2.e+09 3.e+09 figure 5. typical insertion loss esd7361xv2t1g (sod523) figure 6. typical capacitance over frequency esd7361xv2t1g (sod523) capacitance (pf) frequency (hz) s21 (db) frequency (hz) 1.e+07 1.e+08 1.e+09 1 1 1.e+07 figure 7. typical insertion loss esd7361p2t5g (sod923) s21 (db) frequency (hz) figure 8. typical capacitance over frequency esd7361p2t5g (sod923) current (a) frequency (hz) 0.5 0 ?0.5 ?1 ?1.5 ?2 ?2.5 ?3 ?3.5 ?4 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.5 0 ?0.5 ?1 ?1.5 ?2 ?2.5 ?3 ?3.5 ?4 1 1.e+07 1.e+09 2.e+09 3.e+09 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 4.e+09 0.5 0 ?0.5 ?1 ?1.5 ?2 ?2.5 ?3 ?3.5 ?4 1.e+08 1.e+09 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.e+07 1.e+09 2.e+09 3.e+09 4.e+09
esd7361, szesd7361 www. onsemi.com 4 iec 61000?4?2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000?4?2 w aveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 9. iec61000?4?2 spec figure 10. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000?4?2 waveform. since the iec61000?4?2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
esd7361, szesd7361 www. onsemi.com 5 figure 11. positive tlp i?v curve figure 12. negative tlp i?v curve tlp current (a) v c , voltage (v) 25 040 35 30 51015 25 20 tlp current (a) v c , voltage (v) ?25 0 ?14 ?12 ?10 ?2 ?4 ?6 ?8 note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns. v iec is the equivalent voltage stress level calculated at the secondary peak of the iec 61000?4?2 waveform at t = 30 ns with 2 a/kv. see tlp description below for more information. 20 15 10 5 0 ?20 ?15 ?10 ?5 0 transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i?v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 13. tlp i?v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 14 where an 8 kv iec 61000?4?2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i?v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. figure 13. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 14. comparison between 8 kv iec 61000?4?2 and 8 a and 16 a tlp waveforms
esd7361, szesd7361 www. onsemi.com 6 ordering information device package shipping ? ESD7361HT1G sod?323 (pb?free) 3000 / tape & reel esd7361xv2t1g sod?523 (pb?free) 3000 / tape & reel esd7361p2t5g sod?923 (pb?free) 8000 / tape & reel szESD7361HT1G sod?323 (pb?free) 3000 / tape & reel szesd7361xv2t1g sod?523 (pb?free) 3000 / tape & reel szesd7361p2t5g sod?923 (pb?free) 8000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
esd7361, szesd7361 www. onsemi.com 7 package dimensions sod?323 case 477?02 issue h h e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. lead thickness specified per l/f drawing with solder plating. 4. dimensions a and b do not include mold flash, protrusions or gate burrs. 5. dimension l is measured from end of radius. note 3 d 1 2 b e a3 a1 a c note 5 l h e dim min nom max millimeters a 0.80 0.90 1.00 a1 0.00 0.05 0.10 a3 0.15 ref b 0.25 0.32 0.4 c 0.089 0.12 0.177 d 1.60 1.70 1.80 e 1.15 1.25 1.35 0.08 2.30 2.50 2.70 l 0.031 0.035 0.040 0.000 0.002 0.004 0.006 ref 0.010 0.012 0.016 0.003 0.005 0.007 0.062 0.066 0.070 0.045 0.049 0.053 0.003 0.090 0.098 0.105 min nom max inches 1.60 0.063 0.63 0.025 0.83 0.033 2.85 0.112 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
esd7361, szesd7361 www. onsemi.com 8 package dimensions sod?523 case 502 issue e notes: 6. dimensioning and tolerancing per asme y14.5m, 1994. 7. controlling dimension: millimeters. 8. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 9. dimensions d and e do not include mold flash, pro- trusions, or gate burrs. e d ?x? ?y? b 2x m 0.08 x y a h c dim min nom max millimeters d 1.10 1.20 1.30 e 0.70 0.80 0.90 a 0.50 0.60 0.70 b 0.25 0.30 0.35 c 0.07 0.14 0.20 l 0.30 ref h 1.50 1.60 1.70 12 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* e e recommended top view side view 2x bottom view l2 l 2x 2x 0.48 0.40 2x 1.80 dimension: millimeters package outline l2 0.15 0.20 0.25
esd7361, szesd7361 www. onsemi.com 9 package dimensions sod?923 case 514ab issue c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e do not include mold flash, pro- trusions, or gate burrs. dim min nom max millimeters a 0.34 0.37 0.40 b 0.15 0.20 0.25 c 0.07 0.12 0.17 d 0.75 0.80 0.85 e 0.55 0.60 0.65 0.95 1.00 1.05 l 0.19 ref h e 0.013 0.015 0.016 0.006 0.008 0.010 0.003 0.005 0.007 0.030 0.031 0.033 0.022 0.024 0.026 0.037 0.039 0.041 0.007 ref min nom max inches d e c a ?y? ?x? 2 1 dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* see application note and8455/d for more mounting details 1.20 2x 0.25 2x 0.36 package outline b 2x 0.08 xy top view h e side view 2x bottom view l2 l 2x l2 0.05 0.10 0.15 0.002 0.004 0.006 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 esd7361/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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